Module Introduction Protocol Analyzer SVID is a three-wire serial synchronous bus, which is used for transmitting the communication information between a master and a slave. VCLK is a Clock wire, which is used as the Low-voltage Open Drain Pin and driven by the master, and its max. clock is 26.25MHz. And the VDIO is also the Low-voltage Open Drain Pin, too. When the pull-up resistance for the VDIO is 55 ohm more or less, the VDIO can perform the input/output action. In addition, the ALERT pin is available for the Low Level, which is outputted by the slave. Application Field Protocol Analyzer SVID is mainly used for the Power Management. 【DOWNLOAD】