Logic Analyzers-Zeroplus
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Protocol Analyzer
Pulse Width Trigger Module
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Julio Enrique Varela Moraga(Chile)
Julio Enrique Varela Moraga(Chile)

I am really impressed on the performance of your Zero pluls LAP-C logic analyzer, specially on the I2C module which I am currently using.

The system that we are analyzing we design it the year 1998,It is composed of a Master and eight Slaves.The Master has a processor DS87C520 ,and the processing slaves PIC 16F873A

In both processing was simulated by Software all the protocol I2C. In Pic in the processing the implementation was written in Assembler.

Currently we are incorporating a second Bus I2C,using the chip PCA9555.This circuit is mounted in the slaves,and accessed by a second processing AT89C55,mounted in the Master.

In the opportunities that we have attempted to use the module incorporated in the processors PIC (mode i2c),never it has operated adequately,for this motive,we have simulated the protocol I2C in the PIC.