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LAP-F1-64


 

User Manual     Software

General
Free
Protocols -

1-WIRE, CAN 2.0B, IRDA, 3-WIRE, JTAG 2.0, PS/2, I2C (EEPROM 24LCS61/24LCS62), SSI Interface, MANCHESTER, MILLER, SPI Compatible (Atmel Memory), I2C, UART (RS-232C/422/485), SPI, 7-SEGMENT LED, USB 1.1, LCD1602, DIGITAL LOGIC, ARITHMETICAL LOGIC, MICROWIRE, I2C (EEPROM 24L), UP DOWN COUNTER, MICROWIRE (EEPROM 93C), MCU-51 DECODE, General Free Protocols
N/A - USB 2.0
 
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Specifications
Lossless Long Time Record example
 
   
Certifications
  FCC / CE / WEEE / RoHS / REACH
   
Power supply
  AC (IN):100~240V, 50~60Hz DC (OUT):9V / 5.55A
   
Phase error
  < 3 ns
   
Special software features
  .Zooming and panning .Waveform and UI Customization .State list and Waveform view .Packet list .Waveform Navigator .Memory view .Statistic .File Comparison
   
Data transmission
  USB 3.0 (compatible with 2.0)
   
Operating system
  Windows (11 / 10 / 8.1 / 7)
   
Trigger
  .6 protocol triggers (hardware)(serial): I2C, I2S, SPI, SVID, UART(RS-232C/422/485), CAN 2.0B .Trigger types: Pattern / Edge / Pulse-Width / Interval .Trigger channels: 64 .Trigger delay: Yes .Trigger levels: 256 .Trigger pass: 1-65535
   
Memory
 
Memory depth per channel (bits) / channels

4M / 64 ch
8M / 32 ch
16M / 16 ch
32M / 8 ch
64M / 4 ch
128M / 2 ch
256M / 1 ch

64M / 64 ch
128M / 32 ch
256M / 16 ch
512M / 8 ch
1G / 4 ch
256M / 64 ch
512M / 32 ch
1G / 16 ch
512M / 64 ch
1G / 32 ch
   
Active probes / Signals
  P120LV .DUT Bandwidth (Max.):120 MHz .Channels (Max.):Data 64 ch .Signal Type:Single-Ended Bus .Input Impedance / Capacitance:190 Kohm ± 10% / 4.3 pF ±2 pF .Bus Voltage: VIH:0.6V-5V .Input DC Voltage (Max.): ± 10V P200EM (4 ch + 1 ch (CLK) .DUT Bandwidth (Max.):200 MHz .Channels (Max.):Data 32 ch .Signal Type:Single-Ended Bus .Input Impedance / Capacitance:190 Kohm ± 10% / 4.3 pF ±2 pF .Bus Voltage: VIH:0.6V-5V .Input DC Voltage (Max.): ± 10V
   
Sampling rate
  .Internal (Timing)(Asynchronous): Max. 1 GHz .External (State)(Synchronous): Max. 200 MHz (Dual-edge)
   

 

 

 

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