Logic Analysis

Step 1: Double click icon of LAP-32128U-A_STD to run the software

Step 2: Click “OK” to load the last file used or click “Cancel” to create a new file capturing data from the window of LogicAnalyzer appears.

Step 3: When software interface appears, please follow setup process below:

1.      Go to setup “RAM size” which 2K16K32K64K128K are provided. User could select the RAM size meeting requirement. We are selecting 128K here.

2.      Go to setup suitable “sample rate” which should be setup at least four times higher then the frequency of the Oscillator on the device under test. We are selecting 200MHz as sample rate here.

3.      Go to setup “trigger condition” required which Don’t careHighLowRising Edge Falling Edge Either Edge are provided. We are selecting the Rising Edge as trigger condition here.

4.      Go to setup “trigger level” required which TTL CMOS (5V) CMOS (3.3V)ECL and user define (-6V to +6V) are provided. We are selecting TTL here as default value.

Step 4: When above 4 processes are completed, go to click the Single Run  icon to turn on the logic analyzer capturing the data, then turn on the tested device. The logic analyzer is going to capture and calculate signals. As soon as the data has been stored in RAM, then system displays the wave.

Step 5: When the system completes the wave display, then go to click  to show all data which is displayed at better way to be looked.