• ZEROPLUS leading application courses are tailored to L.A. learners. Each participant may get an analyzer with a signal simulation card for practical usage.
  • After class, each participant will get one LAP-C (16032) together with ZEROPLUS characteristic T-shirt. In addition, there will be some good presents for lucky draw!
  • Lunch and refreshments as well as course materials are available during class.
  • Participants are allowed to register the learning program and review again. Those who do not join the program at first time will be exclusive of free lunch and learning material. Meal served with additional fees US$ 7. Meanwhile, raffle tickets will be spared to those who first join the class.
  • Training certificate will be offered for those who complete the application course and are welcome to join ZEROPLUS FB group for further benefits.
  • Courses are ZEROPLUS own designed for engineers to make use of seamlessly in any industry.


To refine engineers’ R & D process and debugging efficiency by operating the analyzer
To explore logic analyzer’s specific functions such as compression,trigger, file comparison, signal filtering, and memory stack, focusing on most frequently discussed busway like I2C, UART, and SPI and putting them into practice during class.
To help participants use oscilloscope and logic analyzer at proper time, we will analyze fundamental ideas and compare the differences in between.
To support participants with the logic analyzer LAP-C(16032) and benefit their learning and working efficiency.

Registration Fees and Remarks

NO. of Enrollment Pricing (US$) Remark
Standard 1 100 Fulfill registration AFTER Mar. 20th (including remittance)
Early Bird 1 70 Fulfill registration BEFORE Mar. 20th (including remittance)
Group Registration 2 80 EXCLUSIVE of the early bird discount
Group Registration 3 or more 70 EXCLUSIVE of the early bird discount

Class Schedule

Date 6/6 10/9
Location Taipei Taipei


Time Duration Subjects Details
09:30 ~ 09:50 20 Registration & tea time
09:50 ~ 10:10 20 Opening speech Richard, ZEROPLUS CEO
10:10 ~ 10:20 10 Product roadmap To have more understanding about ZEROPLUS debug solutions
10:20 ~ 10:50 30 Introduction of ZEROPLUS logic analyzers To find out proper time for making use of the logic analyzers
10:50 ~ 11:20 30 Introduction of LAP-C series To complete system installation of LAP-C
11:20 ~ 11:30 10 Tea break
11:30 ~ 12:00 30 Analytical tips of LAP-C series (I) To find out specific functions, such as compression, multi-machine stacking, trigger level, sampling clock, trigger delay, and trigger count, etc.
12:00 ~ 13:30 90 Lunch time
13:30 ~ 14:00 30 Analytical tips of LAP-C series (II) To find out signal processing and other functions, such as compression, double mode, signal filtering, file comparison, and noise filtering, etc.
14:00 ~ 14:15 15 Tea break
14:15 ~ 15:15 60 Analytical tips of LAP-C series (III) Introduction of analysis of USB 2.0 bus, search of pulse width, and DSO measurement, together with bus decoding of I2C, SMBus, UART, CAN2.0 , and SPI
15:15 ~ 15:30 15 Tea break
15:30 ~ 15:50 20 Introduction of ZEROPLUS high-end logic analyzers Features, functions, and applications of LAP-F1 and Bus Expert I & II
15:50 ~ 16:20 30 Application of ZEROPLUS logic analyzers Features , analytical & debug timing, and analytical tips of the analyzers
16:20 ~ 16:30 10 Case study & group discussion
16:30 ~ 17:00 30 Q & A and lucky draw

Contact Us

Shall you have any questions regarding course registration fees, rescheduling, or any other suggestions related to course scheduling, please do not hesitate to contact us by follows: - Albert Cheng
TEL: (886) 2-6620-2225 ext.272
FB contacts: zeroplus.logic.analyzer/